module rcon(
    input clk,
    input rst_n,
    input nxt_en,
    output reg [7:0]rconout
);  
    wire [7:0]sel1 = {{rconout[6:0]}^{7'b0001101},1'b1};
    wire [7:0]sel2 = {rconout[6:0],1'b0};
    wire [7:0]rcount_r = ({8{rconout[7]}} & sel1 ) | ({8{!rconout[7]}} & sel2 );

    always @ (posedge clk or negedge rst_n)begin
        if(!rst_n)
            rconout <= 8'h01;
        else if(nxt_en)
            rconout <= rcount_r;
        else 
            rconout<=rconout;	
    end

endmodule